Contents of Report

[Data of Report]

Report Number:: TR0768
Date of Registration:: 1992.04
English Title:: PIM/k; A Parallel Inference Machine with a Cache Hierarchy
Japanese Title:: ***
English Author:: H.Sakai,S.Asano,A.Nakase,S.Isobe,H.Muratani,T.Takewaki
Japanese:: ***
Name of Organization to which author belongs:: Toshiba,Toshiba,Toshiba,Toshiba,Toshiba,Toshiba
PDF:: tr0768.pdf

	Abstract	.... 2
1	Introduction	.... 2
2	Motive for applying cache hierarchy to PIM/k	.... 3
2.1	KL1 parallel execution on a shared memory	.... 3
2.2	Applying a cache hierarchy to PIM/k	.... 4
3	Memory architecture	.... 4
3.1	Overview	.... 4
3.2	Design consideration of a hierarchial cache protocol	.... 5
3.3	Replacement algorithm for the second-level cache	.... 8
3.4	Debbuging support	.... 9
4	The effect on the KL1 system software	.... 10
4.1	Overview on the standard KL1 system	.... 10
4.2	Turned KL1 system software	.... 11
5	Current status and preliminary evaluation	.... 12
6	Conclusion	.... 13
7	Acknowledgement	.... 13
8	References	.... 14
	End	.... 15

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