Contents of Report

[Data of Report]

Report Number:: TR0767
Date of Registration:: 1992.04
English Title:: The Unique Features of PIM/k: A Parallel Inference Machine with Hierarchical Cache System
Japanese Title:: ***
English Author:: S.Asano,S.Isobe,H.Sakai
Japanese:: ***
Name of Organization to which author belongs:: Toshiba,Toshiba,Toshiba
PDF:: tr0767.pdf

	Abstract	.... 2
1	Introduction	.... 2
2	Motive of the hierartical Shared- memory Artchitecture	.... 2
3	Overview of PIM/k architecture	.... 3
3.1	Memory architecture	.... 3
3.2	Processsor board	.... 4
4	Software debugging and performance evaluation support	.... 5
4.1	Repeatability of a Parallel Processing	.... 5
4.2	Suspension mechanisms	.... 6
4.3	Long trace with little distortion	.... 6
4.4	Universal event counters	.... 7
5	Cache consisitency Protocol	.... 7
5.1	Write invalidate versus write broadcast	.... 7
5.2	Design considerations of a hierarchical cache protocol	.... 7
5.3	Multi-level-inclusion property	.... 9
5.4	Enhancement of the ownnership	.... 9
5.5	Definiton of states and bus commands	.... 9
5.6	Replacement algorithm	.... 10
5.7	Lock operation	.... 12
5.8	Deadlock	.... 12
5.9	Possible enhancements	.... 13
6	Conclusion	.... 13
	Acknowledgement	.... 14
	References	.... 14
	Appendix; Protocol behavior	.... 15
	End	.... 16

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