| Abstract | .... 2 | |
| 1 | Introduction | .... 2 |
| 2 | Hardware Architecure | .... 2 |
| 2.1 | Tag Architecture | .... 2 |
| 2.2 | Pipeline Organization | .... 2 |
| 2.3 | Pipeline Data Typing and Deference | .... 3 |
| 3 | Layout Design Features | .... 3 |
| 3.1 | Problem of Clock Distribution | .... 3 |
| 3.2 | Clock Strategy | .... 3 |
| 4 | 0.8um Process Technology | .... 3 |
| 5 | Practical Results and Applications | .... 3 |
| 5.1 | Performance | .... 3 |
| 5.2 | Parallel Inference Machine | .... 4 |
| 6 | Conclusion | .... 4 |
| Acknowledgement | .... 4 | |
| References | .... 4 | |
| End | .... 5 |
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