Contents of Report

[Data of Report]

Report Number:: TR0577
Date of Registration:: 1990.08
English Title:: Process Element Architecture for Parallel Inference Machine:PIM/p
Japanese Title:: 並列推論マシンPIM/pの要素プロセッサアーキテクチャ
English Author:: A.Goto,T.Shinogi,T.Chikayama,K.Kumon,A.Hattori
Japanese:: 後藤　厚宏,篠木　剛,近山　隆,久門　耕一,服部　彰
Name of Organization to which author belongs:: ICOT,Fujitsu,ICOT,Fujitsu,Fujitsu
PDF:: tr0577.pdf

	Abstract	.... 4
1	Introduction	.... 5
2	Characteristics of KL1	.... 6
2.1	Brief Introduction to KL1 Abstract Machine	.... 6
2.2	Conditional Execution Features in KL1	.... 7
2.3	Incremental Garbage Collection by MRB	.... 8
3	CPU Architecture Design	.... 9
3.1	Alternatives for KL1-B implementation	.... 9
3.2	Basic Instructions	.... 10
3.3	Tagged Architecture	.... 10
3.4	Macro-call function	.... 12
3.5	Support for Dereference and MRB Garbage Collection	.... 13
4	Cache Architecture Design	.... 14
4.1	Motivations for Cache Design	.... 15
4.2	Cache Protocol	.... 15
4.3	Local Coherent Cache Optimized for KL1	.... 16
5	Processor Element Implementation	.... 17
5.1	Cache System	.... 19
5.2	Registers	.... 19
5.3	CPU Execution Pipeline	.... 20
5.4	Slit-check and Interrupt	.... 21
6	Conclusion	.... 23
	Acknowledgement	.... 24
	References	.... 24
	和文概要	.... 27
	End	.... 30

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