| Abstract | .... 2 | |
| 1 | Introduction | .... 2 |
| 2 | Two Level hierarchical System Structure | .... 2 |
| 3 | High Speed Cluster Architecture | .... 3 |
| 3.1 | PE architecture | .... 3 |
| 3.2 | MacroInstruction Call Mechanism | .... 3 |
| 3.3 | Cache Assist Instructions | .... 4 |
| 3.4 | Simulating Cluster Performance | .... 4 |
| 3.5 | Cluster Performance | .... 5 |
| 4 | Intercluster Network | .... 6 |
| 4.1 | Design Issues | .... 6 |
| 4.2 | Deadlock Free Routing Methods | .... 6 |
| 4.3 | Intercluser Network Simulation | .... 6 |
| 5 | Summary | .... 7 |
| Acknowledgements | .... 7 | |
| References | .... 7 |
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