Contents of Report

[Data of Report]

Report Number:: TR0436
Date of Registration:: 1988.11
English Title:: Design and Performance of a Coherent Cache for Parallel Programming Architecture
Japanese Title:: ***
English Author:: A.Goto,A.Matsumoto,E.Tick
Japanese:: ***
Name of Organization to which author belongs:: ICOT,ICOT,Tokyo Univ.
PDF:: tr0436.pdf

	Abstract	.... 2
1	Introduction	.... 2
2	Motivation for Cache Design	.... 3
2.1	FGHC;Base of KL1	.... 4
2.2	KL1 Architecture	.... 5
2.3	Optimizing Cache Performance	.... 6
3	PIM Cache Protocol	.... 7
3.1	Memory Operations	.... 9
3.2	Specifications of Bus Commands and Responses	.... 10
4	Cache Performance Evaluation	.... 12
4.1	Characteristics of the Benchmark Progarams	.... 12
4.2	Cache Simulation Parameters	.... 14
4.3	Effects of Cache Block Size	.... 15
4.4	Effect of the Cache Capacity	.... 16
4.5	Effect of the Number of PEs	.... 17
4.6	Effect of the Cache Optimizations	.... 18
4.7	Effect of Lock Protocol	.... 19
5	Conclusion	.... 19
	Acknowledgements	.... 20
	References	.... 20
	End	.... 22

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