Contents of Report

[Data of Report]

	Abstract	.... 2
1	Introduction	.... 7
2	Language	.... 9
2.1	OR-Parallel Prolog	.... 9
2.2	AND-Parallel FGHC	.... 11
3	Architectures	.... 13
3.1	Overview	.... 13
3.2	Engine Architecture	.... 13
3.3	Binding Mechanism	.... 14
3.4	Scheduler	.... 15
3.5	Storage Model	.... 17
3.6	Garbage Collection	.... 19
4	Literature Review	.... 20
4.1	KL1 Research Papers	.... 20
4.2	Aurora Reseach Papers	.... 22
4.3	Summary	.... 25
5	Methodology	.... 25
5.1	Timing	.... 27
5.2	High-Level Instrumentation	.... 28
5.3	Low-Level Instrumentation	.... 28
5.4	Benchmark	.... 39
6	Architecture Models	.... 44
6.1	KL1	.... 45
6.2	Aurora	.... 48
7	Timing and High-Level Characteristics	.... 50
8	Memory Referencing Characteristics	.... 57
8.1	Memory References	.... 58
8.2	Bus Traffics	.... 64
9	Cache Performance	.... 67
9.1	Calibration	.... 68
9.2	Results	.... 68
10	Conclusion	.... 71
11	Future Work	.... 77
	Acknowledgements	.... 78
A	Appendix;Prolog Benchmarks	.... 79
B	Appendix;FGHC Benchmarks	.... 101
C	Appendix;Sample Cache Simulator Output	.... 123
	End	.... 139

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