Contents of Report

[Data of Report]

Report Number:: TR0327
Date of Registration:: 1987.11
English Title:: Locally Parallel Cache Design Based on KL1 Momory Access Characteristics
Japanese Title:: ***
English Author:: A.Matsumoto,T.Nakagawa,M.Sato,Y.Kimura,K.Nishida,A.Goto
Japanese:: ***
Name of Organization to which author belongs:: ICOT,ICOT,ICOT,ICOTICOT,ICOT
PDF:: tr0327.pdf

	Abstract	.... 2
1	Introduction	.... 2
2	Parallel Processing in a PIM Cluster	.... 4
2.1	Data Structures in KL1 Execution	.... 4
2.2	Shared Heap Model	.... 4
2.3	Memory Access Characteristics and Requirements for Cache	.... 4
3	Locally Parallel Cache Design for PIM	.... 5
3.1	Key Issues in Write Back Cache Design	.... 5
3.2	Optimization for KL1	.... 6
3.3	Key Issues in Lock Operations of KL1	.... 7
4	Locally Parallel Cache and Lock Mechanisms for PIM Cluster	.... 7
4.1	CPU Commands for Memory Operations	.... 7
4.2	CPU Commands for Lock Operation	.... 9
4.3	Five Cache States	.... 9
4.4	Three Lock States	.... 9
4.5	Bus Commands and a Response for Memory Operations	.... 10
4.6	Bus Commands and a Response for Lock Oparations	.... 10
4.7	Features of the Locally Parallel Cache and Lock Mechanisms	.... 12
5	Evaluation of KL1 Memory Access Characteristics	.... 12
5.1	Evaluation Methodology	.... 12
5.2	Configuration of Locally Parallel Cache	.... 12
5.3	Characteristics of a Benchmark Program	.... 13
5.4	Nominal Bus Usage Ratio and Cache Miss Ratio	.... 14
5.5	Cache Capacity and Nominal Bus Usage Ratio	.... 15
5.6	Memory Access Characteristics of Each Area	.... 16
5.7	Effect of the Number of Processing Elements	.... 17
5.8	Effect of the DW,ER and RP Commands	.... 18
5.9	Analysis of Cache States Snapshot of After Execution	.... 18
6	Conclusions	.... 19
	Acknowledgments	.... 20
	References	.... 20
	End	.... 21

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