| Abstract | .... 2 | |
| 1 | Introduction | .... 2 |
| 2 | Objectives | .... 2 |
| 2.1 | Reduction of Hardware Amount | .... 2 |
| 2.2 | Performance Improvement | .... 3 |
| 2.3 | Multi-Processor System | .... 3 |
| 3 | Architecture | .... 3 |
| 3.1 | Implementing KL0 | .... 3 |
| 3.2 | Data Representation | .... 5 |
| 3.3 | Address Space | .... 5 |
| 3.4 | Instructions | .... 5 |
| 4 | Hardware Design | .... 6 |
| 4.1 | Main Memory | .... 6 |
| 4.2 | Address Translator | .... 7 |
| 4.3 | Cache Memory | .... 7 |
| 4.4 | Data Processing Unit | .... 8 |
| 4.5 | Sequence Controller | .... 9 |
| 4.6 | I/O Devices | .... 10 |
| 5 | Performance Evaluation | .... 10 |
| 6 | Conclusion | .... 11 |
| References | .... 11 |
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