| Abstract | .... 2 | |
| 1 | Introduction | .... 2 |
| 2 | Flat GHC | .... 3 |
| 3 | The Abstract Machine Architecture | .... 4 |
| 4 | Intra-PE Processing | .... 5 |
| 4.1 | The AND-tree | .... 5 |
| 4.2 | Exection of Goals | .... 6 |
| 4.3 | Suspension and Resumption | .... 8 |
| 5 | Inter-PE Processing | .... 9 |
| 5.1 | Memory Management | .... 9 |
| 5.2 | Inter-processor Handling of Goals | .... 9 |
| 6 | Unification | .... 12 |
| 6.1 | Passive Part Unification | .... 12 |
| 6.2 | Active Part Unification | .... 14 |
| 7 | Cocurrent Status and Future Directions | .... 17 |
| Acknowledgements | .... 18 | |
| Notes | .... 18 | |
| References | .... 18 | |
| Appendices | .... 19 | |
| A | Data Types | .... 19 |
| B | Inter-PE Messages | .... 19 |
| End | .... 20 |
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