| Abstract | .... 2 | |
| 1 | Introduction | .... 2 |
| 2 | PSI Architecture | .... 3 |
| 2.1 | Word Format | .... 3 |
| 2.2 | Machione Instructions | .... 3 |
| 2.3 | KL0 | .... 3 |
| 2.4 | Execution Enviroment for KL0 | .... 4 |
| 2.5 | Address Representations | .... 4 |
| 2.6 | Address Translation | .... 4 |
| 2.7 | Multiple Processor | .... 5 |
| 2.8 | Interruption | .... 5 |
| 3 | System Configuration | .... 5 |
| 3.1 | Configuration of the Total System | .... 5 |
| 3.2 | I/O Device | .... 5 |
| 4 | Hardware Design | .... 6 |
| 4.1 | Basic Design Concepts | .... 6 |
| 4.2 | Micro Instructions | .... 7 |
| 4.3 | Data Processing Unit | .... 7 |
| 4.4 | Sequential Contorol Unit | .... 10 |
| 4.5 | Memory Module | .... 11 |
| 4.6 | Hardware Implementation | .... 12 |
| 5 | Firmware Developement | .... 12 |
| 6 | Conclusion | .... 12 |
| Acknowledgements | .... 13 | |
| References | .... 13 |
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